Features: *Members of the Texas Instruments SCOPEE Family of Testability Products* Members of the Texas Instruments WidebusE Family* Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port andBoundary-Scan Architecture* SCOPEE Instruction Set IEEE Standard 1149.1-1990 RequiredInstruc...
SN54ABT18245A: Features: *Members of the Texas Instruments SCOPEE Family of Testability Products* Members of the Texas Instruments WidebusE Family* Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access ...
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Features: PinoutSpecificationsDescriptionThe SN54/74LS147 and SN54/74LS148 are Priority Encoders. ...
PinoutDescriptionThe LS155 and LS156 are Dual 1-of-4 Decoder/Demultiplexers with common Address in...

The SN54ABT18245A scan test devices with 18-bit bus transceivers are members of the Texas Instruments SCOPEE testability integratedcircuit family. SN54ABT18245A supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, SN54ABT18245A is 18-bit noninverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry of SN54ABT18245A can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPEE bus transceivers.
Data flow of SN54ABT18245A is controlled by the direction-control (DIR) and output-enable (OE) inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE can be used to disable the device so that the buses are effectively isolated.
In the test mode, the normal operation of the SCOPEE SN54ABT18245A bus transceivers is inhibited and the test circuitry is enabled to observe and control the input/output (I/O) boundary of the device. When enabled, the test circuitry of SN54ABT18245A performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
Four dedicated test pins of SN54ABT18245A observe and control the operation of the test circuitry: test-data input (TDI), test-data output (TDO), test-mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions of SN54ABT18245A such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54ABT18245A is characterized for operation over the full military temperature range of 55 to 125. The SN74ABT18245A is characterized for operation from 40 to 85.