Features: ` Members of the Texas Instruments SCOPETM Family of Testability Products` Members of the Texas Instruments WidebusTM Family` Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture` SCOPEE Instruction Set IEEE Standard 1149.1-1990 Required In...
SN54ABT18640: Features: ` Members of the Texas Instruments SCOPETM Family of Testability Products` Members of the Texas Instruments WidebusTM Family` Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Acce...
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Features: PinoutSpecificationsDescriptionThe SN54/74LS147 and SN54/74LS148 are Priority Encoders. ...
PinoutDescriptionThe LS155 and LS156 are Dual 1-of-4 Decoder/Demultiplexers with common Address in...

The SN54ABT18640 scan test devices with 18-bit inverting bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, SN54ABT18640 is 18-bit inverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the SN54ABT18640 pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPEE bus transceivers.
Data flow is controlled by the direction-control (DIR) and output-enable (OE) inputs. Data transmission of SN54ABT18640 is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE of SN54ABT18640 can be used to disable the device so that the buses are effectively isolated.
In the test mode, the normal operation of the SCOPEE SN54ABT18640 bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry of SN54ABT18640 can perform boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
Four dedicated test pins of SN54ABT18640 observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs of SN54ABT18640 and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN74ABT18640 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ABT18640 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT18640 is characterized for operation from 40°C to 85°C.