SN54ABT853 Selling Leads, Price trend, SN54ABT853 DataSheet download, circuit diagram from SeekIC.com

Features: ` State-of-the-Art EPIC-II BE BiCMOS Design Significantly Reduces Power Dissipation` ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)` Latch-Up Performance Exceeds 500 mA Per JESD 17` Typical VOLP (Output Ground Bounce) <...

See larger image

SeekIC No. : 004496370 Detail

SN54ABT853: Features: ` State-of-the-Art EPIC-II BE BiCMOS Design Significantly Reduces Power Dissipation` ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 ...

SN54ABT853 Data Sheet

Get Latest Price

Part Number:: SN54ABT853
Supply Ability:: 5000

Price Break

Qty
1~5000

Unit Price
Negotiable

Processing time
15 Days

SeekIC Buyer Protection PLUS - newly updated for 2013!

Escrow Protection.
Guaranteed refunds.
Secure payments.
Learn more >>

Month Sales

268 Transactions

Rating

evaluate (4.8 stars)

Upload time: 2025/12/24

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.

Product Details

Description

Features:

` State-of-the-Art EPIC-II BE BiCMOS Design Significantly Reduces Power Dissipation
` ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
` Latch-Up Performance Exceeds 500 mA Per JESD 17
` Typical VOLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
` High-Drive Outputs (32-mA IOH, 64-mA IOL)
` High-Impedance State During Power Up and Power Down
` Parity-Error Flag With Parity Generator/Checker
` Latch for Storage of Parity-Error Flag
` Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs

Pinout

Connection Diagram

Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, V_O . . . . . . ..0.5 V to 5.5 V
Current into any output in the low state, IO:SN54ABT853 . . . . . . . . . . . . . . . . . . . . . . . . .96 mA
                                                                      SN74ABT853 . . . . . . . . . . . . . . . . . . . . . . . .128 mA
Input clamp current, I_IK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 mA
Output clamp current, I_OK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Package thermal impedance, _JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . .. .104°C/W
                                                                          DW package . . . . . . . . . . . . . . . . . . . . . 81°C/W
                                                                          N package . . . . . . . . . . . . . . . . . . . . . . . .67°C/W
                                                                          PW package . . . . . . . . . . . . . . . . .. .. . . .120°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C

Description

The SN54ABT853 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively isolated. The SN54ABT853 transceivers provide true data at their outputs.

A 9-bit parity generator/checker of SN54ABT853 generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity of SN54ABT853 is a forced error condition that gives the designer more system diagnostic capability.

When VCC is between 0 and 2.1 V, the SN54ABT853 is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor SN54ABT853 is determined by the current-sinking capability of the driver.

SN54ABT853

product image

floor Price/Ceiling Price

Price Break

Month Sales

Rating

Payment Methods

Recent History

Description

Customers Who Bought This Item Also Bought

Test Equipment(3237)

Cable Assemblies(5)

Computers, Office - Components, Accessories(4539)

Power Supplies - Board Mount(3035)

Hardware, Fasteners, Accessories(2239)

Optoelectronics(3638)