SN74ALS992

Supply voltage, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, V_I (OERB, OEQ, CLR, and LE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 7 V
Voltage applied to D inputs and to disabled 3-state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T_A . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C

‡ Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

This SN74ALS992 9-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. In addition, this device provides a 3-state buffer-type output and is easily implemented in parity applications.

The SN74ALS992 nine latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. The Q outputs are in the 3-state condition when the output-enable (OEQ) input is high.

Read back is provided through the output-enable (OERB) input. When OERB is taken low, the data present at the output of the data latches is allowed to pass back onto the input data bus. When OERB is taken high, the output of the data latches is isolated from the D inputs. OERB does not affect the internal operation of the latches; however, precautions should be taken not to create a bus conflict.The SN74ALS992 is characterized for operation from 0°C to 70°C.