Features: *EPICE (Enhanced-Performance Implanted CMOS) Process* Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25* Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25* Contain Four Flip-Flops With Double-Rail Outputs* Applications Include: Buffer/Storage Reg...
SN74LV175A: Features: *EPICE (Enhanced-Performance Implanted CMOS) Process* Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25* Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, ...
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The SN74LV175A devices are quadruple D-type flip-flops designed for 2-V to 5.5-V VCC operation.
These devices SN74LV175A have a direct clear (CLR) input and feature complementary outputs from each flip-flop.
SN74LV175A Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse.
SN74LV175A Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
The SN54LV175A is characterized for operation over the full military temperature range of 55 to 125. The SN74LV175A is characterized for operation from 40 to 85.