STE100A

Industry standard
· IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant
· Support for IEEE802.3x flow control
· IEEE802.3u Auto-Negotiation support for 10BASE-T and 100BASE-TX
· PCI bus interface Rev. 2.2 compliant
· ACPI and PCI power management standard compliant
· Support PC99 wake on LAN

 FIFO
· Provides independent transmission and receiving FIFOs, each 2k bytes long
· Pre-fetches up to two transmit packets to minimize inter frame gap (IFG) to 0.96us
· Retransmits collided packet without reload from host memory within 64 bytes.
· Automatically retransmits FIFO under-run packet with maximum drain threshold until 3rd time retry failure without influencing the registers and transmit threshold of next packet.

The STE10/100 is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application.

STE10/100 was designed with advanced CMOS technology to provide glueless 32-bit bus master interface for PCI bus, boot ROM interface, CSMA/CD protocol for Fast Ethernet, as well as the physical media interface for 100BASE-TX of IEEE802.3u and 10BASE-T of IEEE802.3. The auto-negotiation function is also supported for speed and duplex detection.

The STE10/100 provides both half-duplex and fullduplex operation, as well as support for full-duplex flow control. It provides long FIFO buffers for transmission and receiving, and early interrupt mechanism to enhance performance. The STE10/100 also supports ACPI and PCI compliant power management function.