MFG:ST Package Cooled:TO-220 D/C:04+
MFG: ST
Package Cooled: TO-220
D/C: 04+
Description: Using the latest high voltage MESH OVERLAY] process, STMicroelectronics has designed an advanced famil...
Using the latest high voltage MESH OVERLAY] process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company's proprieraty edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics.
|
Symbol |
Parameter |
Value |
Units |
|
VDS |
Drain-source Voltage (VGS = 0) |
500 |
V |
|
VDGR |
Drain- gate Voltage (RGS = 20 k) |
500 |
V |
|
VGS |
Gate-source Voltage |
±30 |
V |
|
ID |
Drain Current (continuous) at Tc = 25 |
8.6 |
A |
|
ID |
Drain Current (continuous) at Tc = 100 |
5.4 |
A |
|
IDM(•) |
Drain Current (pulsed) |
34.4 |
A |
|
Ptot |
Total Dissipation at Tc = 25 |
125 |
W |
| Derating Factor |
1 |
W/ | |
|
dv/dt (1) |
Peak Diode Recovery voltage slope |
4.5 |
V/ns |
|
VISO |
Insulat ion Withstand Voltage (DC) |
- |
|
|
Tstg |
Storage Temperature |
-65 to +150 |
|
|
Tj |
Max. Operating Junction Temperature |
150 |
|
TYPE |
VDSS |
RDS(on) |
ID |
| STP9NB50 |
500 V |
< 0.85 |
8.6 A |
STP9NB50
PDF/DataSheet Download
This series of POWER MOSFETS STP9NA50FIrepresents the most advanced high voltage technology. The optimized cell layout coupled with a new proprietary edge termination concur to give the device low RDS(on) and gate charge, unequalled ruggedness and superior s...
This series of POWER MOSFETS STP9NA50 represents the most advanced high voltage technology. The optimized cell layout coupled with a new proprietary edge termination concur to give the device low RDS(on) and gate charge, unequalled ruggedness and superior sw...
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