Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 A 3.7 V On-State Drain Currenta ID(on) VDS = 5 V, VGS = 10 V 1170 A Drain...
SUM110N04-2m7H: Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS...
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Features: `TrenchFET® Power MOSFET` 175 Junction Temperature`Optimized for Low-Side Synchronou...
Features: `TrenchFET®Power MOSFET` 175 Junction Temperature` Low Thermal Resistance Package` H...
Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test C...
| SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) | |||||
| Parameter | Symbol | Test Conditions | Simulated Data |
Measured Data |
Unit |
| Static | |||||
| Gate Threshold Voltage | VGS(th) | VDS = VGS, ID = 250 A | 3.7 | V | |
| On-State Drain Currenta | ID(on) | VDS = 5 V, VGS = 10 V | 1170 | A | |
| Drain-Source On-State Resistancea | rDS(on) | VGS = 10 V, ID = 30 A | 0.0022 | 0.0022 | Ω |
| VGS = 10 V, ID = 30 A, TJ = 125°C | 0.0031 | ||||
| VGS = 10 V, ID = 30A, TJ = 175°C | 0.0036 | ||||
| gfs |
VGS = 15V, ID =30 A |
87 |
S | ||
| Forward Voltagea | VSD | IS = 85 A, VGS = 0 V | 1 | 1.1 | V |
| Dynamicb | |||||
| Input Capacitance | Ciss | VGS = 0 V, VDS = 25 V, f = 1 MHz | 12450 | 15720 | Pf |
| Output Capacitance | Coss | 1429 | 1400 | ||
| Reverse Transfer Capacitance | Crss | 786 | 800 | ||
| Total Gate Chargec | Qg | VDS = 30 V, VGS = 10 V, ID = 110 A | 262 | 250 | NC |
| Gate-Source Chargec | Qgs | 95 | 95 | ||
| Gate-Drain Chargec | Qgd | 57 | 57 | ||
| Turn-On Delay Timec | td(on) | VDD = 30 V, RL = 0.27Ω ID= 110A, VGEN = 10 V, RG = 2.5 Ω |
43 | 50 | Ns |
| Rise Timec | tr | 101 | 150 | ||
| Turn-Off Delay Timec | td(off) | 75 | 70 | ||
| Fall Timec | tf | 43 | 25 | ||
The attached spice model of SUM110N04-2m7H describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance of SUM110N04-2m7H is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network of SUM110N04-2m7H is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the SUM110N04-2m7H.