DescriptionThe attached spice model of SUM110P04-05describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance...
SUM110P04-05: DescriptionThe attached spice model of SUM110P04-05describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55...
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Features: `TrenchFET® Power MOSFET` 175 Junction Temperature`Optimized for Low-Side Synchronou...
Features: `TrenchFET®Power MOSFET` 175 Junction Temperature` Low Thermal Resistance Package` H...
Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test C...
The attached spice model of SUM110P04-05 describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance of SUM110P04-05 is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network of SUM110P04-05 is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the SUM110P04-05.