SY100E417

The SY100E417 is a quint LVPECL-to-PECL translator. It can also be used as a quint PECL-to-LVPECL translator. The device receives standard PECL signals and translates them to differential LVPECL output signals (or vice versa). The SY100E417 can also be used as a differential line receiver for PECL-to-PECL or LVPECL-to-LVPECL signals. However, please note that for the latter we will need two different power supplies. Please refer to Function Table for more details.

A VBB output is provided for interfacing single ended input signals. If a single ended input is to be used, the VBB output should be connected to the Dn input and the active signal will drive the Dn input. When used, the VBB should be bypassed to V_CC via a 0.01F capacitor. The VBB is designed to act as a switching reference for the SY100E417 under single ended input conditions. As a result, the pin can only source/sink 0.5mA of current.

To accomplish the PECL-to-LVPECL level translation, the SY100E417 requires three power rails. The V_CC and V_CC_V_BB supply is to be connected to the standard PECL supply, the 3.3V supply is to be connected to the V_CCO supply, and GND is connected to the system ground plane. Both the V_CC and V_CCO should be bypassed to ground with a 0.01F capacitor.

To accomplish the LVPECL-to-PECL level translation, the SY100E417 requires three power rails as well. The 5.0V supply is connected to the V_CC and V_CCO pins, 3.3V supply is connected to the V_CC_V_BB pin and GND is connected to the system ground plane. V_CC_V_BB is used to provide a proper VBB output level if a single ended input is used. V_CC_V_BB = 3.3V is only required for single-ended LVPECL input. For differential LVPECL input, V_CC_V_BB can be either 3.3V or 5.0V.

Under open input conditions, the Dn input will be biased at a VCC/2 voltage level and the Dn input will be pulled to GND. This condition will force the "Qn" output low, ensuring stability.