Si91822

Input Voltage, V_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
SD Input Voltage, V_SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to V_IN
Output Current, I_OUT . . . . . .. . . . . 300 mA Continuous, Short Circuit Protected
Output Voltage, V_OUT . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to V_O(nom) + 0.3 V
Maximum Junction Temperature, T_J(max) .. . .. . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature, T_STG . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 150°C
ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . 2 kV
Power Dissipation (Package)b
8-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 846 mW
Thermal Impedance( JA)
8-Pin MSOPa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 130°C/W
Notes: a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.7 mW/°C above T_A = 25°C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The Si91822 is a 300-mA CMOS LDO (low dropout) voltage regulator. The device features ultra low ground current and dropout voltage to prolong battery life in portable electronics. The Si91822 offers line/load transient response and ripple rejection superior to that of bipolar or BiCMOS LDO regulators. The device is designed to maintain regulation while delivering 600-mA peak current. This is useful for systems that have high surge current upon turn-on. The Si91822 is designed to drive the lower cost ceramic, as well as tantalum, output capacitors. The device is guaranteed stable from maximum load current down to 0-mA load. In addition, an external noise bypass cap acitor connected to the device's C _NOISE pin will lower the LDO's output noise for low noise applications.

The Si91822 also includes an out-of-regulation error flag. When the output voltage is 5% below its nominal output voltage, the error flag output goes low. If a capacitor is connected to the device's delay pin, the error flag output pin will generate a delayed power-on-reset signal.