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Part Number: T2316407A

 

 

 

 

Description: The T2316405A and T2316407A is a randomly accessed solid state memory containing 16,777,216 bits organ...


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T2316407A General Description


The T2316405A and T2316407A is a randomly accessed solid state memory containing 16,777,216 bits organized in a x 4 configuration. It offers Fast Page mode with Extended Data Output (EDO).

During READ or WRITE cycles, each of the 4 memory bits (1 bit per I/O) is uniquely addressed through the 22 address bits, which are entered 11 bits (A0-A10) at a time. RAS latches the first 11 bits and CAS latches the latter 11 bits.

A READ or WRITE cycle is selected with the WE input. A logic HIGH on WE dictates READ mode while a logic LOW on WE dictates WRITE mode. During a WRITE cycle, data -in is latched by the falling edge of WE or CAS , whichever occurs last. When WE goes Low prior to CAS going LOW ( EARLY WRITE cycle), the output pins remain open (High-Z) until the next CAS cycle.

A Late Write or Read-Modify-Write occurs. When WE falls after CAS was taken LOW (Late Write cycle). OE must be taken HIGH to disable the data-outputs prior to applying input data.

The four data inputs and four data outputs are routed through four pins using common I/O, and pin direction is controlled by WE and OE .

T2316407A Maximum Ratings

Parameter
Symbol
Value
Unit
Voltage on Any Pin Relative To Vss
VT
-0.5 to 4.6
V
Supply Voltage Relative To Vss
Vcc
-0.5 to 4.6
V
Short circuit Output Current
Iout
50
mA
Power Dissipation
PT
1
W
Operating Temperature
TOPR
0 to 70
°C
Storage Temperature
Tstg
-55 to 125
°C

T2316407A Features

· Industry-standard x 4 pinouts and timing functions
· power supply : T2316405A 2.6V(±0.2V) T2316407A 3.3V(±0.3V)
· All device pins are TTL- compatible.
· 2048-cycle refresh in 32 ms.
· Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN.
· Extended data-out (EDO) PAGE MODE access cycle.

T2316407A Connection Diagram

T2316407A  Connection Diagram

T2316407A datasheet

T2316407A
PDF/DataSheet Download

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