T35L6464A

The Taiwan Memory Technology Synchronous Burst RAM family employs high-speed, low power CMOS design using advanced triple-layer polysilicon,double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors.

The T35L6464A SRAM integrates 65536 x 64 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable ( CE ), depth-expansion chip enables (CE2 and CE2), burst control inputs (ADSC , ADSP , and ADV ), write enables (BW1 , BW2 , BW3 , BW4 , and BWE ), and global write (GW ).

Asynchronous inputs include the output enable (OE ), Snooze enable (ZZ) and burst mode control (MODE). The data outputs (Q), enabled by OE , are also asynchronous.

Addresses and chip enables are registered with either address status processor (ADSP ) or address status controller (ADSC ) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV ).

Address and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BW1 controls DQ1-DQ8. BW2 controls DQ9-DQ16. BW3 controls DQ17-DQ 24. BW4 controls DQ25-DQ32. BW1 , BW2 , BW3 , and BW4 can be active only with BWE being LOW. GW being LOW causes all bytes to be written. WRITE pass-through capability allows written data available at the output for the immediately next READ cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance.