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THC63LVD103

Features: • Wide dot clock range: 8-135MHz suited for NTSC,VGA, SVGA, XGA,SXGA and SXGA+• PLL requires no external components• Supports spread spectrum clock generator• On chip jitter filtering• Clock edge selectable• Supports reduced swing LVDS for low EMI̶...

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SeekIC No. : 004518646 Detail

THC63LVD103: Features: • Wide dot clock range: 8-135MHz suited for NTSC,VGA, SVGA, XGA,SXGA and SXGA+• PLL requires no external components• Supports spread spectrum clock generator• On ch...

THC63LVD103 Data Sheet

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Part Number:
THC63LVD103
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/27

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Product Details

Description



Features:

• Wide dot clock range: 8-135MHz suited for NTSC,VGA, SVGA, XGA,SXGA and SXGA+
• PLL requires no external components
• Supports spread spectrum clock generator
• On chip jitter filtering
• Clock edge selectable
• Supports reduced swing LVDS for low EMI
• Power down mode
• Low power single 3.3V CMOS design
• 64pin TQFP
• Backward compatible with




Specifications

Supply Voltage (VCC) -0.3V ~ +4.0V
CMOS/TTL Input Voltage -0.3V ~ (VCC + 0.3V)
CMOS/TTL Output Voltage -0.3V ~ (VCC + 0.3V)
LVDS Driver Output Voltage -0.3V ~ (VCC + 0.3V)
Junction Temperature +125 °C
Storage Temperature Range -55°C ~ +150 °C
Resistance to soldering heat +260 /10sec °C
Maximum Power Dissipation @+25 °C 1.0W

1. "Absolute Maximum Ratings" are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical  haracteristics" specify conditions for device operation.




Description

The THC63LVD103 transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA+ resolutions.

The THC63LVD103 converts 35bits of CMOS/TTLdata into LVDS(Low Voltage Differential Signaling) data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin.

At a transmit clock frequency of 135MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC, VSYNC, DE, CNTL1, CNTL2) are transmitted at an effective rate of 945Mbps per LVDS channel.




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