Features: Built-in quartz with digital trimming andtemperature compensation facilities INTEL and MOTOROLA interface compatibility 15 ns typical access time at 5.0V 1.2 A typical standby current at 3.0VWide supply voltage range, 2.0 VDD 5.5V Integrated battery switch-over Battery voltage range, ...
V3025: Features: Built-in quartz with digital trimming andtemperature compensation facilities INTEL and MOTOROLA interface compatibility 15 ns typical access time at 5.0V 1.2 A typical standby current at ...
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Schottky (Diodes & Rectifiers) 30 Amp 200 Volt Dual TrenchMOS
Parameter | Symbol | Conditions |
Maximum voltage at VDD and VBAT |
VSUPmax | VSS + 7.0V |
Max. voltage at remaining pins | VSUP | VDD + 0.3V |
Min. voltage on all pins | Vmin | VSS 0.3V |
Maximum storage temperature | TSTOmax | +125 |
Minimum storage temperature | TSTOmin | -55 |
Maximum electrostatic discharge to MIL-STD-883C method 3015.7 with ref. to VSS |
VSmax | 1000V |
Maximum soldering conditions | TSmax | 250 x 10s |
Shock resistance | 5000 g. 0.3ms, ½ sine |
Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction
The V3025 is a low power CMOS real time clock with an integrated battery switch-over. The standby current is typically 2.5 A and the access time is 50 ns. The interface is a multiplexed address and data 8 bits bus. Multiplexing of address and data is handled by the input line A /D. There are no busy flags in the V3025, internal time update cycles are invisible to the user's software. Time data can be read from the V3025 in 12 or 24 hour data formats. An external signal puts the V3025 in standby mode. Even in standby, the V3025 pulls the IRQ pin active low on an internal alarm interrupt. Calendar functions include leap year correction and week number calculation. The V3025 can be synchronized to an external 50 Hz signal or to the nearest second or minute. The integrated battery switch-over supply the real time clock part by VDD as long as VDD is higher than VBAT. When VDD decreases under VBAT, the output PFO comes active and the real clock is supplied by the battery or the supercap.