VM5621

The VM5621 has the following features including Encodes and Decodes IBM (2,7) Code;48 Mbits/sec Maximum Code Rate;Soft-Sector 2T Frequency Address Mark Generation;Preamble lock time=64 .T (T=one period of 2F clock);4T (1000...) Preamble Frequency Detection;Differential ECL Drivers and Receivers for Clock and Data;Interface Lines;Available in a 28-lead PLCC Package.

The (2,7) Encoder/Decoder (ENDEC) performs the encoding and decoding necessary to use the (2,7,1,2,4) Run-Length Limited (RLL) code for disk drive memory systems.The ENDEC also performs many other functions such as writing of an address mark for soft sectored disk formats, and the reading of a preamble pattern (PLL sync field) that is compatible with the (2,7) RLL code. The ENDEC is fabricated using a high-speed ECL 2.5 bipolar process.This is the encoded (2,7) write data in RZ format. It drives the Read/Write amplifier circuit.  A high level pulse returning to zero is output for each 'one' that is to be written on the disk's media.This address mark actually violates the (2,7) RLL constraints. Instead of detecting a gap, the VM5621 will write a 2T frequency address mark but is not capable of detecting the address mark. An external circuit is required for 2T address mark detection.

A read operation of VM5621 is initiated by asserting READ-GATE (low) with AME high. At this time, the LTDATA timer circuit begins to count 2f clock pulses and the data separator IC begins locking to the preamble sync field. LTDATA remains false for 64 2f clock cycles after READ GATE is asserted. After the timer has completed its count, LTDATA is asserted and the LTDATA output goes low, the decoder synchronizes itseH to the preamble sync field (4T pattern), and the read data is decoded.Refer to the control timing diagrams.This is a control output which signifies that a minimum length of a preamble pattern has been read. This output may be used to switch the Data Separator circuit from a high to a low tracking rate mode. The output is active low.