W25P022A

Features: · Synchronous operation· High-speed access time: 6/7 nS (max.)· Single +3.3V power supply· Individual byte write capability· 3.3V LVTTL compatible I/O· Clock-controlled and registered input· Asynchronous output enable· Pipelined/non-pipelined data output capability· Supports snooze mode ...

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SeekIC No. : 004544520 Detail

W25P022A: Features: · Synchronous operation· High-speed access time: 6/7 nS (max.)· Single +3.3V power supply· Individual byte write capability· 3.3V LVTTL compatible I/O· Clock-controlled and registered inpu...

floor Price/Ceiling Price

Part Number:
W25P022A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/28

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Product Details

Description



Features:

· Synchronous operation
· High-speed access time: 6/7 nS (max.)
· Single +3.3V power supply
· Individual byte write capability
· 3.3V LVTTL compatible I/O
· Clock-controlled and registered input
· Asynchronous output enable
· Pipelined/non-pipelined data output capability
· Supports snooze mode (low-power state)
· Internal burst counter supports Intel burst mode & linear burst mode
· Supports both 2T/2T & 2T/1T mode
· Packaged in 100-pin QFP or TQFP



Pinout

  Connection Diagram


Specifications

PARAMETER RATING UNIT
Core Supply Voltage to Vss -0.5 to +4.6 V
I/O Supply Voltage to Vss -0.5 to +4.6 V
Input/Output to VSS Potential VSSQ -0.5 to VDDQ +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150 °C
Operating Temperature 0 to +70 °C




Description

The W25P022A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM organized as 65,536 ´ 32 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentiumä burst mode and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode reduces power dissipation.

The W25P022A supports both 2T/2T mode and 2T/1T mode, which can be selected by pin 42. The default mode is 2T/1T, with pin 42 low. To switch to 2T/2T mode, bias pin 42 to VDDQ. The state of pin 42 should not be changed after power up. The 2T/2T mode will sustain one cycle of valid data output in a burst read cycle when the device is deselected by CE2/ CE3 . This mode supports 3-1-1-1- 1-1-1-1 in a two-bank, back-to-back burst read cycle. On the other hand, the 2T/1T mode disables data output within one cycle in a burst read cycle when the device is deselected by CE2/ CE3 . In this mode, the device supports only 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.




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