ZL30119

• Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813
• Internal APLL provides standard output clock frequencies from 6.48 MHz up to 622.08 MHz with jitter less than 1 ps RMS for OC-48/STM-16 interfaces
• Programmable output synthesizers (P0, P1) generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz
• Provides two DPLLs which are independently configurable through a serial peripheral interface
• DPLL1 provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth
• DPLL2 provides a comprehensive set of features for generating derived output clocks and other general purpose clocks
• Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz
• Provides 3 sync inputs for output frame pulse alignment
• Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency
• Configurable input to output delay, and output to output phase alignment
• Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities
• Supports IEEE 1149.1 JTAG Boundary Scan

The ZL30119 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and ynchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses.