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ZL30406

Features: • Meets jitter requirements of Telcordia GR-253- CORE for OC-48, OC-12, and OC-3 rates• Meets jitter requirements of ITU-T G.813 for STM- 16, STM-4 and STM-1 rates• Provides four LVPECL differential output clocks at 77.76 MHz• Provides a CML differential clock pro...

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SeekIC No. : 004550960 Detail

ZL30406: Features: • Meets jitter requirements of Telcordia GR-253- CORE for OC-48, OC-12, and OC-3 rates• Meets jitter requirements of ITU-T G.813 for STM- 16, STM-4 and STM-1 rates• Provi...

ZL30406 Data Sheet

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Part Number:
ZL30406
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Meets jitter requirements of Telcordia GR-253- CORE for OC-48, OC-12, and OC-3 rates
• Meets jitter requirements of ITU-T G.813 for STM- 16, STM-4 and STM-1 rates
• Provides four LVPECL differential output clocks at 77.76 MHz
• Provides a CML differential clock programmable to 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz
• Provides a single-ended CMOS clock at 19.44 MHz
• Provides enable/disable control of output clocks
• Accepts a CMOS reference at 19.44 MHz
• 3.3 V supply


Application

• SONET/SDH line cards
• Network Element timing cards


Pinout

Connection Diagram


Specifications

  Parameter Symbol Min.‡ Max.‡ UNIT
1 Supply voltage VDDR, VCCR TBD TBD V
2 Voltage on any pin VPIN -0.5 VCC + 0.5
VCC + 0.5		 V
3 Current on any pin IPIN -0.5 30 mA
4 ESD Rating VESD   1500 V
5 Storage temperature TST -55 150
6 Package power dissipation PPD   1.8 W

† Voltages are with respect to ground unless otherwise stated.
‡ Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.



Description

The ZL30406 is an analog phase-locked loop (APLL) designed to provide rate conversion and jitter attenuation for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30406 generates very low jitter clocks that meet the jitter requirements of Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1 rates and ITU-T G.813 STM-16, STM-4 and STM-1 rates.

The ZL30406 accepts a CMOS compatible reference at 19.44 MHz and generates four LVPECL differential output clocks at 77.76 MHz, a CML differential clock programmable to 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz and a single-ended  CMOS clock at 19.44 MHz. The output clocks can be individually enabled or disabled.




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