ZL50021GAC

The ZL50021GAC is designed as a maximum 4,096 x 4,096 channel non-blocking digital Time Division Multiplex (TDM) switch. It has thirty-two input streams (STi0-31) and thirty-two output streams (STio0-31). The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream.

ZL50021GAC has eight main features. (1)4096-channel x 4096-channel non-blocking digital time division multiplex (TDM) switch at 8.192 and 16.384Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or 16.384Mbps. (2)32 serial TDM input, 32 serial TDM output streams. (3)Integrated digital phase-locked loop (DPLL) exceeds telcordia GR-1244-CORE stratum 3 specifications. (4)Output clocks have less than 1 ns of jitter (except for the 1.544MHz output). (5)DPLL provides holdover, freerun and jitter attenuation features with four independent reference source inputs. (6)Programmable key DPLL parameters (filter corner frequency, locking range, auto-holdover hysteresis range, phase slope, lock detector range). (7)Exceptional input clock cycle to cycle variation tolerance (20ns for all rates). (8)Output streams can be configured as bidirectional for connection to backplanes. That are all the main features of ZL50021GAC .

Some absolute maximum ratings of ZL50021GAC have been concluded into several points as follow. (1)Its IO supply voltage would be min -0.5V and max 5.0V. (2)Its core supply voltage would be min -0.5V and max 2.5V. (3)Its input voltage would be min -0.5V and max Vdd+0.5V. (4)Its input voltage (5V tolerant inputs) would be min -0.5V and max 7.0V. (5)Its continuous current at digital outputs would be max 15mA. (6)Its package power dissipation would be max 1.5W. (7)Its storage temperature range would be from -55°C to +125°C. It should be noted that stresses above those listed in absolute maximum ratings may cause permanent damage to device. And so on. If you have any question or suggestion or want to know more information of ZL50021GAC please contact us for details. Thank you!