STLC60134S, STLC60134STR, STLC60135 Selling Leads, Datasheet
MFG:ST Package Cooled:QFP D/C:09+
STLC60134S, STLC60134STR, STLC60135 Datasheet download

Part Number: STLC60134S
MFG: ST
Package Cooled: QFP
D/C: 09+
MFG:ST Package Cooled:QFP D/C:09+
STLC60134S, STLC60134STR, STLC60135 Datasheet download

MFG: ST
Package Cooled: QFP
D/C: 09+
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Datasheet: STLC60134S
File Size: 170963 KB
Manufacturer: STMICROELECTRONICS [STMicroelectronics]
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PDF/DataSheet Download
Datasheet: STL100NH3LL
File Size: 493880 KB
Manufacturer: STMICROELECTRONICS [STMicroelectronics]
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PDF/DataSheet Download
Datasheet: STLC60135
File Size: 194185 KB
Manufacturer: STMICROELECTRONICS [STMicroelectronics]
Download : Click here to Download
STLC60134S is the Analog Front End of the STMicroelectronics Tosca] ADSL chipset and when coupled with TLC60135 (DTM modem) allows to get a T1.413 Issue 2 compliant solution.
The STLC60134S analog front end handles 2 transmission channels on a balanced 2 wire interconnection;a 16 to 640Kbit/s upstream channel and a 1.536 to 8.192Mbit/s downstream channel.
A 256 carrier DMT coding (frequency spacing 4.3125kHz) transforms the downstream channel to a 1MHz bandwidth analog signal (tones 32-255) and the upstream channel (tones 8-31) to a 100kHz bandwidth signal on the line.
This asymmetrical data transmission system uses high resolution, high speed analog to digital and digital to analog conversion and high order analog filtering to reduce the echo and noise in both the ATU-C/ATU-R receivers and transmitters. External low noise driver and input stage used with STLC60134Sguarantee low noise performances.
The STLC60134S chip can be used at ATU-C and ATU-R ends (behaviour set by LTNT pin).The selection consists mainly of a filter interchange between the RX and TX path. The filters (with a programmable cutoff frequency) use automatic Continuous Time Tuning to avoid time varying phase characteristic which can be of dramatic consequencefor DMT modem. It requires few external components, uses a 3.3V supply (a separate 3.0V supply of the digital part is possible)and is packaged in a 64-pin TQFP in order to reduce PCB area.
| Symbol | Parameter | Min | Max | Unit |
| VDD | Any VDD Supply Voltage, related to substrate | - 0.5 | 5 | V |
| Vin | Voltage at any input pin | -0.5 | VDD +0.5 | V |
| Tstg | Storage Temperature | -40 | 125 | |
| TL | Lead Temperature (10 second soldering) | 300 | ||
| ILU | Latch - up current @80 | 100 | mA | |
| IAVDD | Analog Supply Current @ 3.6V - normal operation | 30 | mA | |
| IAVDD | Analog Supply Current @ 3.6V - power down | 56 | mA | |
| IDVDD | Analog Supply Current @ 3.6V - normal operation | 56 | mA | |
| IDVDD | Analog Supply Current @ 3.6V - power down | 50 |

The STLC60135 is the DMT modem and ATM framerof theSTMicroelectronics Tosca] chipset.When coupled with STLC60134 analog front-end and an external controller running dedicated firmware,the product fulfils ANSI T1.413 "Issue 2"DMT ADSL specification.
The STLC60135 may be used at both ends of ADSL loop: ATU-C and ATU-R. The chip supports UTOPIA level 1 and UTOPIA level 2 interface and a non ATM synchronous bit-stream interface.
The STLC60135 can be splitted up into two different sections. The physical one performs the DMT modulation, demodulation, Reed-Solomon encoding,bit interleaving and 4D trellis coding.
The ATM section embodies framing functions for the generic and ATM Transmission Convergence (TC) layers. The generic TC consists of data scrambling and Reed Solomon error corrections,with and without interleaving.
The STLC60135 is controlled and programmed by an external controller (ADSL Transceiver Controller,ATC) that sets the programmable coefficients.
The firmware controls the initialization phase and carries out the consequent adaptationoperations.
| Symbol | Parameter | Min | Typ | Max | Unit |
| VDD | Supply Voltage | 3.0 | 3.3 | 3.6 | V |
| Ptot | Total Power Dissipation | 900 | 1400 | mW | |
| Tamb | Ambient Temperature 1m/s airflow | -40 | 85 |
DTM modem for ADSL, compatible with the following standards:
ANSI T1.413 Issue 2
ITU-T G.992.1 (G.dmt)
ITU-T G.992.2 (G.lite)
Same chip for both ATU-C and ATU-R
Supports either ATM (Utopia level 1 & 2) or bitstream interface
16 bit multiplexed microprocessor interface (little and big endian compatibility)
Analog Front End management
Dual latency paths: fast and interleaved
ATM's PHY layer: cell processing (cell delineation,cell insertion, HEC)
ADSL's overhead management
Reed Solomon encode/decode
Trellis encode/decode(Viterbi)
DMT mapping/ demapping over 256 carriers
Fine (2ppm) timing recover using Rotor and Adaptative Frequency Domain Equalizing
Time Domain Equalization
Front end digital filters
0.35mmHCMOS6 Technology
144 pin PQFP package
Power Consumption 1 Watt at 3.3V

