ADC

Published:2009/7/5 21:10:00 Author:May | From:SeekIC

Conversion speed of this design is the sum of the delay through the comparator and the decoding gates. Reference voltages for each bit are developed from a precision resistor ladder network. Values of R and 2R are chosen so that the threshold is 1/2 of the least significant bit. This assures maximum accuracy of ±1/2 bit. The individual strobe line and duality features of the NE521 greatly reduced the cost and complexity of the design.



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