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AV9107C-13

Features: · Patented on-chip Phase-Locked Loop with VCO for clock generation· Provides two synthesized clocks· Generates 20 and 40 MHz output frequencies.· On-chip loop filter· Low power CMOS technology· Single +3.3 or +5 volt power supply· 8-pin SOIC packagePinoutSpecificationsAVDD, VDD reference...

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SeekIC No. : 004291796 Detail

AV9107C-13: Features: · Patented on-chip Phase-Locked Loop with VCO for clock generation· Provides two synthesized clocks· Generates 20 and 40 MHz output frequencies.· On-chip loop filter· Low power CMOS techno...

AV9107C-13 Data Sheet

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Part Number:
AV9107C-13
Supply Ability:
5000

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  • 1~5000
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Product Details

Description



Features:

· Patented on-chip Phase-Locked Loop with VCO
  for clock generation
· Provides two synthesized clocks
· Generates 20 and 40 MHz output frequencies.
· On-chip loop filter
· Low power CMOS technology
· Single +3.3 or +5 volt power supply
· 8-pin SOIC package


Pinout

Connection Diagram


Specifications

AVDD, VDD referenced to GND . . . . . . . . . . . . . .  . . . . . . . .  .. . . . 7V
Operating temperature under bias. . . . . . . .  . . . . . . . 0°C to +70°C
Storage temperature . . . . . . . . . . . . . . . . . ... . . . . -65°C to +150°C
Voltage on I/O pins referenced to GND. . . . GND -0.5V to VDD +0.5V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect product reliability.


Description

The AV9107C-13 offers a tiny footprint solution for generating two simultaneous clocks. The AV9107C-13 uses a 20 MHz crystal to generate two PLL synthesis outputs of 20 and 40 MHz. The Output enable pin will tristate the 40 MHz output when low (maintaining the 20 MHz output runing in both logic levels). The power pin takes the device to a low current condition, shutting off the PLL and forcing both outputs low, when the PD# pin is low. There is a built-in pull-up on both the OE and PD# inputs.

The AV9107C-13 has advanced features which include on-chip loop filters, tristate outputs, and power-down capability. A minimum of external components - two decoupling capacitors and an optional ferrite bead - are all that are required for jitterfree operation.




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