DP83256

Features: Single chip FDDI Physical Layer (PHY) solutionIntegrated Digital Clock Recovery Module provides enhanced tracking and greater lock acquisition rangeIntegrated Clock Generation Module provides all necessary clock signals for an FDDI system from an external 125 MHz referenceAlternate PMD I...

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SeekIC No. : 004327934 Detail

DP83256: Features: Single chip FDDI Physical Layer (PHY) solutionIntegrated Digital Clock Recovery Module provides enhanced tracking and greater lock acquisition rangeIntegrated Clock Generation Module provi...

floor Price/Ceiling Price

Part Number:
DP83256
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/26

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Product Details

Description



Features:

Single chip FDDI Physical Layer (PHY) solution
Integrated Digital Clock Recovery Module provides enhanced tracking and greater lock acquisition range
Integrated Clock Generation Module provides all necessary clock signals for an FDDI system from an external 125 MHz reference
Alternate PMD Interface (DP83256-AP57) supports UTP twisted pair FDDI PMDs with no external clock recovery or clock generation functions required
No External Filter Components
Connection Management (CMT) Support (LEM TNEPC React CF React Auto Scrubbing)
Full on-chip configuration switch
Low Power CMOS-BIPOLAR design using a single 5V supply
Full duplex operation with through parity
Separate management interface (Control Bus)
Selectable Parity on PHY-MAC Interface and Control Bus Interface
Two levels of on-chip loopback
4B/5B encoderdecoder
Framing logic
Elasticity Buffer Repeat Filter and Smoother
Line state detectorgenerator
Supports single attach stations dual attach stations
and concentrators with no external logic
DP83256 for SASDAS single path stations
DP83257 for SASDAS singledual path stations
DP83256-AP for SASDAS single path stations that require the alternate PMD interface




Pinout

  Connection Diagram


Specifications

Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCC
SupplyVoltage
 
-0.5
 
70
V
DCIN
InputVoltage
 
-0.5
 
VCC +0.5
V
DCOUT
OutputVoltage
 
-0.5
 
VCC+ 0.5
V
 
VCCESDtootherVCC
MaximumVoltage
Differential
 
 
 
0.3
V
 
StorageTemperature
 
-65
 
150
ECL
SignalOutputCurrent
 
 
 
-50
mA
 
ESDProtection
 
2000
 
 
V
 



Description

The DP8325656-AP57 Enhanced Physical Layer Controller (PLAYER +device) implements one complete Physical Layer (PHY) entity as defined by the Fiber Distributed Data Interface (FDDI) ANSI X3T95 standard

The PLAYER +device DP8325656-AP57 integrates state of the art digital clock recovery and improved clock generation functions to
enhance performance eliminate external components and remove critical layout requirements

FDDI Station Management (SMT) is aided by Link ErrorMonitoring support Noise Event Timer (TNE) support Optional Auto Scrubbing support an integrated configuration switch and built-in functionality designed to remove all stringent response time requirements such as PC React and CF React


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