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Part Number: FDG6320C

 

MFG: FAIRCHILD

 

D/C: 08+

Description: These dual N & P-Channel logic level enhancement mode field effect transistors are produced using ...


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FDG6320C General Description


These dual N & P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.

FDG6320C Maximum Ratings

Symbol
Parameter
N-Channel
P-Channel
Units
VDSS
VGSS
Drain-Source Voltage
Gate-Source Voltage
25
8
0.22
0.65
-25
-8
-0.14
-0.4
V
V
A

W

°C
kV
ID
Drain Current - Continuous - Pulsed

PD

Power Dissipation for Single Operation (Note 1)
0.3
-55 to 150
6
TJ,TSTG
ESD
Operating and Storage Temperature Ranger
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)

FDG6320C Features

·N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 W @ VGS= 4.5 V, RDS(ON)  = 5.0 W @ VGS= 2.7 V.
·P-Ch -0.14 A, -25V, RDS(ON)  = 10 W @ VGS= -4.5V, RDS(ON)  = 13 W @ VGS= -2.7V.
·Very small package outline SC70-6.
·Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V).
·Gate-Source Zener for ESD ruggedness (>6kV Human Body Model).

FDG6320C Connection Diagram

FDG6320C  Connection Diagram

FDG6320C datasheet

FDG6320C
PDF/DataSheet Download

  • Datasheet: FDG6320C
  • File Size: 200989 KB
  • Manufacturer: FAIRCHILD [Fairchild Semiconductor]
  • Click here to Download

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