Purchase GAL26CLV12, In-stock GAL26CLV12 From SeekIC.
Part Number: GAL26CLV12
Description: The GAL26CLV12D, at 5 ns maximum propagation delay time, provides higher performance than its 5V count...
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GAL26CLV12
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DataSheet
General Description
GAL26CLV12 General Description
The GAL26CLV12D, at 5 ns maximum propagation delay time, provides higher performance than its 5V counterpart. The GAL26CLV12D can interface with both 3.3V and 5V signal levels. The GAL26CLV12D is manufactured using Lattice Semiconductor's advanced 3.3V E2 CMOS process, which combines CMOS with Electrically Erasable (E2 ) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility byallowing the Output Logic Macrocell (OLMC) to be configured by the user.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and function- ality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
GAL26CLV12 Maximum Ratings
Supply voltage VCC .................................... -0.5 to +4.6V
Input or I/O voltage applied ....................... -0.5 to +5.6V
Off-state output voltage applied ................ -0.5 to +4.6V
Storage Temperature ................................... -65 to 150
Ambient Temperature with
Power Applied ........................................... -55 to 125
1.Stresses above those listed under the "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress only
ratings and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of
this specification is not implied (while programming, follow the
programming specifications).
Input or I/O voltage applied ....................... -0.5 to +5.6V
Off-state output voltage applied ................ -0.5 to +4.6V
Storage Temperature ................................... -65 to 150
Ambient Temperature with
Power Applied ........................................... -55 to 125
1.Stresses above those listed under the "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress only
ratings and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of
this specification is not implied (while programming, follow the
programming specifications).
GAL26CLV12 Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- 5 ns Maximum Propagation Delay
- Fmax = 200 MHz
- 3.5 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE
- JEDEC-Compatible 3.3V Interface Standard
- Inputs and I/O Interface with Standard 5V TTL Devices
• ACTIVE PULL-UPS ON ALL PINS
• E2CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• TWELVE OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- Glue Logic for 3.3V Systems
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
- 5 ns Maximum Propagation Delay
- Fmax = 200 MHz
- 3.5 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE
- JEDEC-Compatible 3.3V Interface Standard
- Inputs and I/O Interface with Standard 5V TTL Devices
• ACTIVE PULL-UPS ON ALL PINS
• E2CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• TWELVE OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- Glue Logic for 3.3V Systems
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
GAL26CLV12 Connection Diagram
GAL26CLV12
PDF/DataSheet Download
- Datasheet: GAL26CLV12
- File Size: 230980 KB
- Manufacturer: LATTICE [Lattice Semiconductor]
- Click here to Download
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