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Description: The Hitachi HM51(S)4260C is CMOS dynamic RAM organized as 262,144-word*16-bit. HM51(S)4260C has realized higher density...


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HM51S4260C General Description


The Hitachi HM51(S)4260C is CMOS dynamic RAM organized as 262,144-word*16-bit. HM51(S)4260C has realized higher density, higher performance and various functions by employing 0.8 mm CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4260C offers fast page mode as a high speed access mode. Multiplexed address input permits the HM51(S)4260C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. Internal refresh timer enables HM51S4260C self refresh operation.

HM51S4260C Maximum Ratings

Parameter Symbol Value Unit
Voltage on any pin relative to VSS VT 1.0 to +7.0 V
Supply voltage relative to VSS VCC 1.0 to +7.0
V
Short circuit output current Iout 50 mA
Power dissipation PT 1.0 W
Operating temperature Topr 0 to +70
Storage temperature Tstg 55 to +125

HM51S4260C Features

• Single 5 V (±10%) (HM51(S)4260C-6/7/8)
(±5%) (HM51(S)4260C-6R)
• High speed
- Access time: 60 ns/70 ns/80 ns (max)
• Low power dissipation
- Active mode: 825 mW/788 mW/770 mW/688 mW (max)
- Standby mode: 11 mW (max) (HM51(S)4260C-6/7/8)
10.5 mW (max) (HM51(S)4260C-6R)
1.1 mW (max) (L-version) (HM51(S)4260C-6/7/8)
1.05 mW (max) (L-version) (HM51(S)4260C-6R)
• Fast page mode capability
• 512 refresh cycles: 8 ms 128 ms (L-version)
• 2 CAS -byte control
• 2 variations of refresh
- RAS -only refresh
- CAS -before-RAS refresh
• Battery backup operation (L-version)
• Self refresh operation (HM51S4260C)

HM51S4260C Connection Diagram

HM51S4260C  Connection Diagram

HM51S4260C datasheet

HM51S4260C
PDF/DataSheet Download

  • Datasheet: HM51S4260C
  • File Size: 267043 KB
  • Manufacturer: HITACHI [Hitachi Semiconductor]
  • Click here to Download

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