IDT5992A

The IDT5992A is a high fanout PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal.

The IDT5992A has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels.

The IDT5992A maintains Cypress CY7B992 compatibility while providing two additional features: Synchronous Output Enable (GND/sOE), and Positive/Negative Edge Synchronization (VDDQ/PE). When the GND/ sOE pin is held low, all the outputs are synchronously enabled (CY7B992 compatibility).

However, if GND/sOE is held high, all the outputs except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when the VDDQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input (CY7B992 compatibility). When VDDQ/PE is held low, all the outputs are synchronized with the negative edge of REF.