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Part Number: M5M5Y5672TG 25
Description: The M5M5Y5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit. It is de...
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M5M5Y5672TG 25
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DataSheet
General Description
M5M5Y5672TG 25 General Description
The M5M5Y5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5Y5672TG operates on a single 1.8V power supply and are 1.8V CMOS compatible.
M5M5Y5672TG 25 Maximum Ratings
|
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
|
VDD |
Power Supply Voltage |
With respect to VSS |
-0.5*~2.5 |
V |
|
VDDQ |
I/O Buffer Power Supply Voltage |
-0.5*~2.5 |
V | |
|
VI |
Input Voltage |
-0.5~VDDQ+0.5(2.5V max.) ** |
V | |
|
VO |
Output Voltage |
-0.5~VDDQ+0.5(2.5V max.) ** |
mA | |
|
PD |
Maximum Power Dissipation (VDD) |
1072.5 |
mW | |
|
TOPR |
Operating Temperature |
0~70 |
||
|
TSTG(bias) |
Storage Temperature(bias) |
-10~85 |
||
|
Tstg |
Storage Temperature |
-65~150 |
** This is -1.0V~VDDQ+1.0V(3.6V max.) when pulse width2ns, and 0.5V~VDDQ+0.5V in case of DC.
M5M5Y5672TG 25 Features
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 250, 225, and 200 MHz
• Fast access time: 2.6, 2.8, 3.2 ns
• Single 1.8V +150/-100mV power supply VDD
• Separate VDDQ for 1.8V I/O
• Individual byte write (BWa# - BWh#) controls may be tied LOW
• Single Read/Write control pin (W#)
• Echo Clock outputs track data output drivers
• ZQ mode pin for user-selectable output drive strength
• 2 User programmable chip enable inputs for easy depth expansion
• Linear or Interleaved Burst Modes
• JTAG boundary scan support
• Fast clock speed: 250, 225, and 200 MHz
• Fast access time: 2.6, 2.8, 3.2 ns
• Single 1.8V +150/-100mV power supply VDD
• Separate VDDQ for 1.8V I/O
• Individual byte write (BWa# - BWh#) controls may be tied LOW
• Single Read/Write control pin (W#)
• Echo Clock outputs track data output drivers
• ZQ mode pin for user-selectable output drive strength
• 2 User programmable chip enable inputs for easy depth expansion
• Linear or Interleaved Burst Modes
• JTAG boundary scan support
M5M5Y5672TG 25 Typical Application
High-end networking products that require high bandwidth, such as switches and routers.
M5M1
PDF/DataSheet Download
- Datasheet: M5M1
- File Size: 183622 KB
- Manufacturer: ETC [ETC]
- Click here to Download
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The M5M5Y5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high p...
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The M5M5Y5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high p...
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