MC88PL117

The 88PL117 provides the necessary clock frequencies for the PowerPC 601 and Pentium Microprocessors. With
output frequency capabilities up to 120MHz and the ability to also generate half and quarter frequency clocks the 88PL117 simplifies the system implementation of a PowerPC 601 or Pentium Microprocessor. This section will overview the clock requirements of the PowerPC 601 and Pentium Microprocessors and apply those to the specification limits of
the 88PL117 to demonstrate compatibility. Although not exhaustive the intent is to provide a basic set of guidelines on ystem implementation. For more cost sensitive applications which require fewer clocks the designer should refer to the MC88915TFN133 data sheet for an alternative clock driver suitable for PowerPC 601 or Pentium Microprocessor based designs.

Figures 7 and 8 illustrate two common output config urations of the 88PL117 which will facilitate POWERPC 601
(MPC601) system designs. Figure 7 would prove beneficial for high frequency processor designs where the bus clock
would likely run at one fourth the 2X_PCLK input. In this configuration a 2X_Q output of the 88PL117 can drive the
2X_PCLK of the PowerPC 601 processor while a Q and Q/2 output can drive the PCLK_ENand BCLK_ENinputs
respectively. For designs where the system bus will run at half the frequency of the 2X_PCLK (same frequency as the
internal processor clock) a larger number of Q outputs would be required. Figure 8 could be used in this situation with a 2X_Q output driving the 2X_PCLK input and a Q output driving the PCLK_EN. In this implementation the BCLK_EN
input of the MPC601 is simply tied LOW. drive the BCLK_ENinput. The Qj output can be phase delayed relative to the 2X_Q output to ensure the hold time requirement of the MPC601 processor will be met.