SM8211M

Conforms to POCSAG standard for pagers
512 or 1200 bps signal speed
Supports tone, numeric or character call messages
Battery-saving function for low battery consumption
BS1 (RF control main output signal) and BS3 (PLL setup signal) 60-step setup time setting-for BS3, 50.8 ms (max) at 1200 bps and 119.1 ms (max) at 512 bps Note that (BS3 setup time) - (BS1 setup time) should be set to  2.
BS2 (RF DC-level adjustment signal) before/during reception selectable adjustment timing
 6 addresses *4 sub-addresses (total of 24 addresses)
1-bit and 2-bit burst error auto-correction function (messages only)
25 to 75% duty factor signal coverage (during preamble detection)
8 rate error detection condition settings
8 receive mode settings
76.8 or 153.6 kHz system clock (crystal oscillator or external clock input)
Built-in oscillator capacitor
Built-in input signal filter, with filter ON/OFF and 4 selectable filter characteristics
1.2 to 3.5 V (76.8 kHz system clock) or 2.0 to 3.5 V (153.6 kHz system clock) operating supply voltage
Molybdenum-gate CMOS process realizes low power dissipation
20-pin SSOP

The SM8211M is a POCSAG-standard (Post Office Code Standardization Advisory Group) signal processor LSI, which conforms to CCIR recommendation 584 concerning standard international wireless calling codes.

The SM8211M supports call messages in either tone, numerical or character outputs at signal speeds of 512 bps or 1200 bps using a 76.8 kHz system clock, or 2400 bps using a double-speed 153.6 kHz system clock. Note that output timing values for 2400 bps mode operation are not shown in this datasheet, but can be obtained by halving the values for 1200 bps mode operation.

CMOS structure and low-voltage operation realize low power dissipation, plus an intermittent-duty receive method (battery-saving function) reduces battery consumption.

The SM8211M is available in 20-pin SSOPs.