SUM60N10-17

Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 A 3.2 V On-State Drain Currenta ID(on) VDS5 V, VGS = 10 V 366 A Drain-Sou...

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SeekIC No. : 004509318 Detail

SUM60N10-17: Specifications SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions SimulatedData MeasuredData Unit Static Gate Threshold Voltage VGS(th) VDS = VGS...

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Part Number:
SUM60N10-17
Supply Ability:
5000

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  • 1~5000
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  • 15 Days
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Upload time: 2025/12/23

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Description



Specifications

SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions Simulated
Data
Measured
Data
Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 A 3.2 V
On-State Drain Currenta ID(on) VDS5 V, VGS = 10 V 366 A
Drain-Source On-State Resistancea rDS(on) VGS = 10V, ID =30A 0.013 0.013
VGS = 6V, ID =20A 0.015 0.015
VGS = 10 V, ID = 30A, TJ = 125°C 0.024

VGS = 10 V, ID = 30A, TJ = 175°C

0.030
Forward Voltagea VSD IF=30A, VGS = 0 V 0.90 1 V
Dynamicb
Input Capacitance Ciss VGS = 0 V, VDS = 25 V, f = 1 MHz 4377 4300 pF
Output Capacitance Coss 482 450
Reverse Transfer Capacitance Crss 239 175
Total Gate Chargec Qg VDS =50 V, VGS = 10 V, ID =60A 57 65 nC
Gate-Source Chargec Qgs 25 25
Gate-Drain Chargec Qgd 19 19
Turn-On Delay Timec td(on) VDD =50V, RL = 1.5
ID60A, VGEN = 10 V, RG = 2.5
25 15 ns
Rise Timec tr 12 12
Turn-Off Delay Timec td(off) 17 30
Fall Timec tf 10 10
Source-Drain Reverse Recovery Time trr IF = 50A, di/dt = 100 A/µs 110 125





Description

The attached spice model of SUM60N10-17 describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance of SUM60N10-17 is best fit at the gate bias near the threshold voltage.

A novel gate-to-drain feedback capacitance network of SUM60N10-17 is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the SUM60N10-17.






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