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GLT5160L16-7TC, GLT5160L16P-70TC, GLT5640L16

Table of contents:
Info of GLT5160L16-7TC
Info of GLT5160L16P-70TC
Info of GLT5640L16

GLT5160L16-7TC, GLT5160L16P-70TC, GLT5640L16 Selling Leads, Datasheet

MFG:G-LINK Package Cooled:TSSOP D/C:03+

GLT5160L16-7TC, GLT5160L16P-70TC, GLT5640L16 Picture

GLT5160L16-7TC, GLT5160L16P-70TC, GLT5640L16 Datasheet download

Five Points

Part Number: GLT5160L16-7TC

MFG: G-LINK

Package Cooled: TSSOP

D/C: 03+

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GLT5640L16 General Description

The GLT5640L16 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 1,048,576 x 16 x 4 (word x bit x bank), respectively.

The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture and clock frequency up to 183MHz. All input and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.

GLT5640L16 Maximum Ratings

Parameter	Symbol	Conditions	Value	Unit
Supply Voltage	V_DD	with respect to VSS	-0.5 to 4.6	V
Supply Voltage for Output	V_DDQ	with respect to VSSQ	-0.5 to 4.6	V
Input Voltage	V_I	with respect to VSS	-0.5 to VDD+0.5	V
Output Voltage	V_O	with respect to VSSQ	-0.5 to VDDQ+0.5	V
Short circuit output current	I_O		50	mA
Power dissipation	P_D	Ta = 25 °C	1	W
Operating temperature	T_OPT		0 to 70
Storage temperature	T_STG		-65 to 150

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be
operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.

GLT5640L16 Features

• Single 3.3V ((±0.3V) power supply
• High speed clock cycle time -5.5:183MHz<3-3-3>,-6:166MHz<3-3-3>, -7:143MHz<3-3-3>,
-8: 125MHz<3-3-3> -10 : 100MHz<3-3-3>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by BA0 & BA1 (Bank Select)
• Byte control by LDQM and UDQM
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• Burst termination by Burst stop and Precharge command

GLT5640L16 Connection Diagram

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