Purchase GAL20VP8, In-stock GAL20VP8 From SeekIC.
Part Number: GAL20VP8
Description: The GAL20VP8, with 64 mA drive capability and 15 ns maximum propagation delay time is ideal for Bus an...
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GAL20VP8
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DataSheet
General Description
GAL20VP8 General Description
The GAL20VP8, with 64 mA drive capability and 15 ns maximum propagation delay time is ideal for Bus and Memory control applications. The GAL20VP8 is manufactured using Lattice Semiconductor's advanced E2CMOS process which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
System bus and memory interfaces require control logic before driving the bus or memory interface signals. The GAL20VP8 combines the familiar GAL20V8 architecture with bus drivers as its outputs. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The 64mA output drive eliminates the need for additional devices to provide bus-driving capability.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
GAL20VP8 Maximum Ratings
Supply voltage VCC ......................................... .5 to +7V
Input voltage applied .......................... 2.5 to VCC +1.0V
Off-state output voltage applied ......... 2.5 to VCC +1.0V
Storage Temperature .................................. 65 to 150
Ambient Temperature with
Power Applied ............................................. 55 to 125
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to
the device. These are stress only ratings and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied
(while programming, follow the programming specifications).
Input voltage applied .......................... 2.5 to VCC +1.0V
Off-state output voltage applied ......... 2.5 to VCC +1.0V
Storage Temperature .................................. 65 to 150
Ambient Temperature with
Power Applied ............................................. 55 to 125
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to
the device. These are stress only ratings and functional operation of the device at these or at any
other conditions above those indicated in the operational sections of this specification is not implied
(while programming, follow the programming specifications).
GAL20VP8 Features
• HIGH DRIVE E2CMOS® GAL® DEVICE
- TTL Compatible 64 mA Output Drive
- 15 ns Maximum Propagation Delay
- Fmax = 80 MHz
- 10 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
• ENHANCED INPUT AND OUTPUT FEATURES
- Schmitt Trigger Inputs
- Programmable Open-Drain or Totem-Pole Outputs
- Active Pull-Ups on All Inputs and I/O pins
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Architecturally Compatible with Standard GAL20V8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- Ideal for Bus Control & Bus Arbitration Logic
- Bus Address Decode Logic
- Memory Address, Data and Control Circuits
- DMA Control
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
- TTL Compatible 64 mA Output Drive
- 15 ns Maximum Propagation Delay
- Fmax = 80 MHz
- 10 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
• ENHANCED INPUT AND OUTPUT FEATURES
- Schmitt Trigger Inputs
- Programmable Open-Drain or Totem-Pole Outputs
- Active Pull-Ups on All Inputs and I/O pins
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Architecturally Compatible with Standard GAL20V8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- Ideal for Bus Control & Bus Arbitration Logic
- Bus Address Decode Logic
- Memory Address, Data and Control Circuits
- DMA Control
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
GAL20VP8 Connection Diagram
GAL20VP8
PDF/DataSheet Download
- Datasheet: GAL20VP8
- File Size: 269690 KB
- Manufacturer: LATTICE [Lattice Semiconductor]
- Click here to Download
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