SAA2502

· Low sampling frequency decoding possibilities (24 kHz, 22.05 kHz and 16 kHz) of MPEG2 are supported
· A variety of output formats are supported: I2S, SPDIF and 256 or more times oversampled bit serial analog stereo
· Automatic internal dynamic range compression algorithm using programmable compression parameters
· Non byte-aligned coded input data is handled
· Built-in provisions to generate high quality sampling clocks for all six supported sampling frequencies; these sampling clocks may locked to an external PLL to support an extensive list of input data reference clock frequencies
· Bit-rate and sampling-rate settings may be overruled by the microcontroller while the SAA2502 is trying to establish frame synchronization
· Input interface mode which requests data based on input buffer content, enables the handling of variable bit-rate input streams and input data offered in (fixed length) bursts
· An interrupt output pin which can generate interrupt requests at the occurrence of various events; consequently polling by the microcontroller is not needed in most situations
· L3 and the I2C-bus microcontroller interface protocols are supported
· The control interface is always fully operational (also while STOP is asserted)
· CRC protection of scale factors is provided for all supported sample frequencies.

Notes
1. Input voltage should not exceed 6.5 V unless otherwise specified.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor with a rise time of 15 ns.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor.

The SAA2502 is a second generation ISO/MPEG audio source decoder. The device specification has been enhanced with respect to the SAA2500 and SAA2501 ICs and therefore it offers in principle all features of its predecessors.

SAA2502 supports layer I and II of MPEG1 and the MPEG2 requirements for a stereo decoder.